1. Field of the Invention
The present invention relates to a four quadrant multiplying circuit that can be driven at a low power supply voltage.
2. Background Art
A multiplying circuit is one of the commonly known integrated circuits which are used in many fields, particularly, modulating and demodulating circuits.
The output Z from the multiplying circuit satisfies the relationship Z=K.multidot.XY (K=constant) with respect to inputs X and Y. In particular, a multiplying circuit which satisfies the above relationship including signs, regardless of whether the inputs X and Y are positive or negative, is called a four quadrant multiplying circuit.
FIG. 7 is a circuit diagram of a conventional four quadrant multiplying circuit 400. In the following description, the gate voltage of a P-channel or N-channel MOSFETn (n: reference number; same applies hereinafter) is expressed as Vg.sub.n ; the source voltage thereof is expressed as Vs.sub.n ; the gate-source voltage thereof is expressed as Vgs.sub.n ; and the drain current thereof is expressed as Id.sub.n. The threshold voltage of a P-channel MOSFETn is expressed as Vth(P).sub.n and the threshold voltage of an N-channel MOSFETn is expressed as Vth(N).sub.n. Hereinafter, the P-channel MOSFETn is referred to as PMOSn and the N-channel MOSFETn is referred to as NMOSn. Furthermore, in the drawings, circuits 401 to 407 which perform specific functions are surrounded by a dotted line.
The constant-current circuit 407 is constituted by PMOS 1, 2, 3 and 5. PMOS 2, 3 and 5 form a current mirror with PMOS 1, and each output a uniform drain current ld.sub.2, ld.sub.3 and Id.sub.5, respectively. The drain current ld.sub.2 from PMOS 2 is supplied to the source of PMOS 11 and 12. The drain current ld.sub.3 from PMOS 3 is supplied to the source of PMOS 40, 41, 42 and 43. The drain current from PMOS 5 is supplied to the source of PMOS 17 and 18.
The P-channel voltage compression circuit 401 is constituted by PMOS 11, 12, 13 and 14 and it reduces the voltage of an input voltage Vin(a) from an input signal source 51 and a reference voltage Vref1 outputs from a reference voltage power supply 59 (where Vref1=1/2 Vcc) by a predetermined ratio, and outputs source voltages Vs.sub.13 and Vs.sub.14, obtained by compressing the voltage difference vin(a) between input voltage Vin(a) and reference voltage Vref1, to the gates of PMOS 20 and 23 and PMOS 21 and 22.
The P-channel voltage compression circuit 402 is constituted by PMOS 15, 16, 17 and 18, and it reduces the voltage of an input voltage Vin(b) from an input signal source 51 and a reference voltage Vref1 output from a reference voltage power supply 59 by a predetermined ratio, and output source voltages Vs.sub.5 and Vs.sub.16, obtained by compressing the voltage difference vin(b) between input voltage Vin(b) and reference voltage Vref1, to the gates of PMOS 42 and 43 and PMOS 40 and 41.
The current converting circuit 406 is constituted by PMOS 40, 41, 42 and 43 and it converts the uniform drain current ld.sub.3 output by PMOS 3 in accordance with the input voltage Vin(b) and then outputs the converted current. The drain current ld.sub.40 from PMOS 40 is input to the source of PMOS 20 and 21. The drain current ld.sub.41 from PMOS 41 is input to the source of PMOS 24 and 25. The drain current ld.sub.42 from PMOS 42 is input to the source of PMOS 26 and 27. The drain current ld.sub.43 from PMOS 43 is input to the source of PMOS 22 and 23.
A first voltage converting circuit 403 is constituted by PMOS 20, 21 and diffused resistances 53 and 54, and it amplifies the difference between the source voltage Vs.sub.13 and Vs.sub.14 output by the aforementioned P-channel voltage compression circuit 401 and outputs the result to the gates of PMOS 24 and 25.
A second voltage converting circuit 404 is constituted by PMOS 22 and 23 and diffused resistances 57 and 58 and it amplifies the difference between the source voltages Vs.sub.13 and Vs.sub.14 output by the aforementioned P-channel voltage compression circuit 401 and outputs the result to the gates of PMOS 26 and 27.
A Gilbert cell 405 is constituted by PMOS 24, 25, 26 and 27 and diffused resistances 55 and 56. The Gilbert cell 405 multiplies the outputs of the first voltage converting circuit 403 and second voltage converting circuit 404, and outputs the result of this multiplication as the difference between the output voltage Vout(+) in diffused resistance 55 and the output voltage Vout(-) in diffused resistance 56.
FIG. 8 is a graph showing drain current Id and drain-source voltage Vds characteristics for a MOSFET. When the drain-source voltage Vds is below a specific value (.vertline.Vgs.vertline.-.vertline.Vth(P) or Vth(N).vertline.), then the drain current Id rises as the voltage Vds increases. Generally, this region is known as the triode region. Furthermore, when the drain-source voltage Vds is above the aforementioned specific value, the drain current Id has a constant value. This is generally known as the pentode region.
In order that the four quadrant multiplying circuit 400 having the foregoing construction operates properly, it is necessary for all of the MOSFETs making up this circuit 400 to operate in the pentode region.
If PMOS 17 is operating in the pentode region, then a voltage smaller than Vref1+Vth(P).sub.40 or 41 will be supplied to the gates of PMOS 40 and 41. Therefore, the drain voltage Vd.sub.40 of PMOS 40, that is, the source voltages Vs.sub.20, and Vs.sub.21 to PMOS 20 and 21, will be smaller than Vg.sub.40 -Vth(P).sub.40 =Vref1.
If PMOS 18 is operating in the pentode region, then a voltage smaller than Vin(b)+Vth(P).sub.42 or 43 will be supplied to the gates of PMOS 42 and 43. Therefore, the drain voltage Vd.sub.43 from PMOS 43, that is, the source voltages Vs.sub.22 and Vs.sub.23 to PMOS 22 and 23 is smaller than Vg.sub.43 -Vth(P).sub.43 -Vth(P).sub.43 =Vin(b)=Vref1+vin(b).
If PMOS 11 is operating in the pentode region, then a voltage smaller than Vin(a)+Vth(P).sub.11 is supplied to the gates of PMOS 20 and 23.
If PMOS 12 is operating in the pentode region, then a voltage smaller than Vref1+Vth(P).sub.12 is supplied to the gates of PMOS 21, 22.
If the reference voltage Vref1 (=1/2 Vcc) has a small value, then the value of the gate-source voltages Vgs.sub.20 to Vgs.sub.23 for PMOS 20 to 23 will also become small, and it will become difficult to make these gate-source voltages Vgs.sub.20 to Vgs.sub.23 rise above the threshold voltages Vth(P).sub.20 to Vth(P).sub.23 such that the PMOS 20 to 23 are activated.
Therefore, with the four quadrant multiplying circuit 400 of conventional construction, it has been difficult to operate at a low power supply voltage Vcc.